This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, an integrated circuit (IC) having components of a computing system provided on a single chip typically refers to system on a chip (SoC). The SoC is fabricated to include digital, analog, mixed-signal, and/or radio-frequency (RF) capability on a single chip substrate. SoC applications are useful for mobile electronic devices due to their low power consumption and minimal area impact in embedded systems.
In some applications, an SOC may include embedded memory, such as, e.g., static random access memory (SRAM). Due to a denser layout, SRAM may have a higher defect density than other logic circuits, and to improve yield of SRAM, redundant SRAM cells may be provided. SRAM cells may be arranged in an array pattern, and redundant cells are provided as a column or row in the same array as memory cell instances. For SRAM in an SOC, column redundancy is sufficient; however, if accumulated density of SRAM is large, then row redundancy may be used.
Unfortunately, due to conventional layouts, only one defective or faulty row of SRAM memory cells are repairable with one row of redundant memory cells. As such, in conventional technology, if a memory cell array has multiple defective or faulty memory cells on different rows, then only one of the defective or faulty rows is repairable.